This application relates generally to techniques in voltage manipulation in semiconductor devices such as two- or three-dimensional non-volatile semiconductor memory, and more particularly to an analog-to-digital converter (ADC) and a method for digitizing voltages used in the memory.
Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as a small form factor card, has recently become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products. Unlike RAM (random access memory) that is also solid-state memory, flash memory is non-volatile, and retains its stored data even after power is turned off. Also, unlike ROM (read only memory), flash memory is rewritable similar to a disk storage device. In spite of the higher cost, flash memory is increasingly being used in mass storage applications.
Flash EEPROM is similar to EEPROM (electrically erasable and programmable read-only memory) in that it is a non-volatile memory that can be erased and have new data written or “programmed” into their memory cells. Both utilize a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) that must be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions. Flash memory such as Flash EEPROM allows entire blocks of memory cells to be erased at the same time.
The floating gate can hold a range of charges and therefore can be programmed to any threshold voltage level within a threshold voltage window. The size of the threshold voltage window is delimited by the minimum and maximum threshold levels of the device, which in turn correspond to the range of the charges that can be programmed onto the floating gate. The threshold window generally depends on the memory device's characteristics, operating conditions and history. Each distinct, resolvable threshold voltage level range within the window may, in principle, be used to designate a definite memory state of the cell.
In order to improve read and program performance, multiple charge storage elements or memory transistors in an array are read or programmed in parallel. Thus, a “page” of memory elements are read or programmed together. In existing memory architectures, a row typically contains several interleaved pages or it may constitute one page. All memory elements of a page are read or programmed together.
Nonvolatile memory devices are also manufactured from memory cells with a dielectric layer for storing charge. Instead of the conductive floating gate elements described earlier, a dielectric layer is used. An ONO dielectric layer extends across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. For example, a nonvolatile memory cell may have a trapping dielectric sandwiched between two silicon dioxide layers. Multi-state data storage is implemented by separately reading the binary states of the spatially separated charge storage regions within the dielectric.
In order to provide the voltages for memory operations such as the programming and verify operations, as well as any read operations, a voltage generator capable of generating the various DC voltage levels on demand is required. Furthermore, the operations mostly depend on the thresholds of the FET and EEPROM devices making up the circuits and the memory cells. The thresholds of these FET and EEPROM devices changes with temperature. In order to maintain regularity in operation, a common type of these devices need to be supplied with an operating voltage that has a negative temperature coefficient.
United States Patent Publication No. 2004/0062085 A1 discloses an on-chip voltage generator having such capabilities. The voltage generator is implemented with analog circuitry, which occupies substantial space on the chip.
United States Patent Publication No. 2008/0031066 A1 and United States Patent Publication No. 2008/0159000 A1 both disclose on-chip voltage generators that are also analog.
“A 3 bit/Cell 32 Gb NAND Flash Memory at 34 nm with 6 MB/s Program Throughput and with Dynamic 2b/Cell Blocks Configuration Mode for a Program Throughput increase up to 13 MB/s”, ISSCC 2010 Conference, Session 24, DRAM and FLASH MEMORIES, 24.7, Digest of Technical Papers, pp. 444-445, discloses a voltage generator with a digital component where the computation involves looking up values from various stored tables.
Existing voltage generators involve the use of digital to analog converters and associated circuitry to add and subtract voltages with and without temperature coefficients to generate final voltages with negative temperature coefficients. These implementations tend to be expensive, complex, resource intensive and bulky.
U.S. Pat. No. 8,334,796 discloses an on-chip DC voltage generator for generating linear DC voltages with a programmable negative temperature coefficient. The ADC used is a standard flash ADC. However, in practice the flash ADC is non-linear due to non-uniformity of the individual comparators in the ADC.
Therefore there is a general need for an on-chip voltage generator which is compact and inexpensive to implement and flexible in terms of programmability. In particular, a need for an on-chip voltage generator that has a highly linear ADC.